This invention relates to digital multiplication circuits, and more particular to digital multiplication circuits for use with a microprocessor in which the digital multiplication circuit is controlled by a domino control circuit.
A major limitation in the use of field effect transistor circuits and in particular, of large scale integration circuits, is the restriction associated with extending dynamic logic circuits, such as those found in a multiplier, to high-speed applications due to the necessity of multiple clocks that are required for the implementation of logic circuits with field effect transistors. Traditionally, there have been multiple clock phases required for the implementation of field effect transistor logic circuits. A precharge phase is necessary to precharge all of the data lines that interconnect the transistors used to configure the logic circuits and a second clock phase is required to evaluate the results of the implementation of the logic functions. In the cases where the logic circuits are connected together and each stage is dependent on the results of a preceding logic stage, there is a requirement for multi-phase clock functions. A first clock phase precharges all of the data lines for all of the logic circuits; a second clock phase evaluates the first logic level after which the results are applied to a second logic level which is evaluated by a third clock phase and so on through the total number of logic levels. Thus, for an N logic level function to be implemented by field effect transistor circuits, there is a requirement for N+1 clock phases, a phase to precharge all of the data lines, and a phase for each logic level to be evaluated by. The time slot ordering of the logic levels thus results in many of the logic circuits idily waiting for their turn to be evaluated with the overall consequence being that these circuits are exceptionally slow. This has traditionally not been a problem in the cases where the field effect transistor logic circuits are used for a hand-held calculator or other such applications. However, as more complicated requirements for the circuits develop, the need for speed in implementing complex logic functions becomes critical. The luxury of having circuits waiting for the appropriate time slots to be evaluated is not possible in applications that require high speed, nanosecond range, operation.
In copending application, Ser. No. 520,880, filed on Aug. 5, 1983, entitled "A Multi-Level Logic System" and assigned to Assignee of the present invention, there was disclosed the use of a multi-level logic system that incorporates a dummy load clock evaluation circuit for each stage.
The minimization of time in a microprocessor system that is required to implement multiplication functions may be reduced from many processing cycles of the microprocessor to a relative few number of microprocessor cycles through the implementation of a hardware multiplier that implements the modified Booth algorithm of digital multiplication. However, even this reduction in time is not sufficient to provide a field effect transistor type microprocessor with the speed necessary for modern technical applications.